Semiconductor dies (i.e., chips) may comprise memory, logic, sensors, etc. A semiconductor die may be utilized singly, or may be utilized in combination with other semiconductor dies. In some applications, two or more semiconductor dies may be combined in a single packaged assembly. FIG. 1 shows an example prior art packaged assembly 10 which comprises a pair of semiconductor dies 12a and 12b. The dies may be identical to one another, or may be different relative to one another. The dies 12a and 12b may be referred to as a top die and a bottom die, respectively, in that the die 12a is above the die 12b. 
Each of the dies 12a, 12b has a face side 14 and a bottom side 16, with the face side comprising most of the significant circuitry. Each of the dies also has a so-called M3 pad 11a, 11b, which is an interconnection region associated with the die. The M3 pad 11a, 11b of each die is part of a redistribution wiring layer (RDL) 15a, 15b that extends along the face of the die and couples with wires (or other suitable connections) 19a, 19b. The redistribution wiring layer 15a, 15b of each die 12a, 12b may be considered to include redistribution wiring 18a, 18b and the M3 pad 11a, 11b coupled with such redistribution wiring 18a, 18b. 
The M3 pads 11a, 11b may be utilized for testing of the dies, and it may be desired to have access to the M3 pads 11a, 11b in order to ascertain integrity of each die before completion of the packaged assembly 10. For instance, it may be desired that the M3 pads 11a, 11b be of sufficient size and be otherwise suitably accessible for coupling with an access probe at some time prior to completion of the packaged assembly 10 so that each of the dies 12a and 12b may be tested. The dies 12a, 12b may then be repaired or replaced if found to be unsatisfactory, prior to finalization of the packaged assembly 10.
The dies are supported by a substrate 20. Such substrate has interconnects 22 (indicated to be package balls) on an exterior of the package 10. The interconnects 22 may comprise solder balls, or any other structure suitable for electrically coupling the package 10 with circuitry external of the package. Also, additional interconnects extend through the substrate (such additional interconnects are not shown) and electrically couple the interconnects 22 with circuitry associated with the dies 12a and 12b. Such additional interconnects may, for example, electrically couple the wires 19a, 19b with the interconnects 22, and may thereby electrically couple the wires 19a, 19b (and associated redistribution wiring layers 15a, 15b) with circuitry external of the package 10.
The dies 12a, 12b may comprise any suitable semiconductor material, and in some embodiments may comprise silicon.
The substrate 20 may comprise any suitable material, and in some embodiments may comprise a polymeric circuit board.
An insulative material 24 extends over and between the dies 12a and 12b. Such insulative material may comprise any suitable composition or combination of compositions.
The assembly 10 of FIG. 1 has each of the dies 12a and 12b in a face-up orientation, and provides a separate connection 19 from the redistribution wiring layers to circuitry associated with the substrate 20 (such circuitry is not shown in FIG. 1, but is known to persons of ordinary skill).
FIG. 2 shows the prior art construction of FIG. 1 in a more simplistic view so that relevant relationships may be more clearly understood. Specifically, each of the semiconductor dies 12, 12b is shown to include a redistribution wiring layer 15a, 15b; and the redistribution wiring layers 15a, 15b are shown to couple to circuitry associated with the substrate 20 through the wires 19a, 19b. 
It would be desirable to develop improved multi-die assemblies configured to enable suitable access to M3 pads (or equivalent interconnection regions), and which enable rapid electrical access to the semiconductor dies within the assemblies.